• RP2350 Datasheet
  • Colophon
    • Legal disclaimer notice
    • Table of contents
  • Chapter 1. Introduction
    • 1.1. The Chip
    • 1.2. Pinout Reference
      • 1.2.1. Pin Locations
      • 1.2.2. Pin Descriptions
      • 1.2.3. GPIO Functions (Bank 0)
      • 1.2.4. GPIO Functions (Bank 1)
    • 1.3. Why is the chip called RP2350?
  • Chapter 2. System Bus
    • 2.1. Bus Fabric
      • 2.1.1. Bus Priority
      • 2.1.2. Bus Security Filtering
      • 2.1.3. Atomic Register Access
      • 2.1.4. APB Bridge
      • 2.1.5. Narrow IO Register Writes
      • 2.1.6. Global Exclusive Monitor
      • 2.1.7. Bus Performance Counters
    • 2.2. Address Map
      • 2.2.1. ROM
      • 2.2.2. XIP
      • 2.2.3. SRAM
      • 2.2.4. APB Registers
      • 2.2.5. AHB Registers
      • 2.2.6. Core-local Peripherals (SIO)
      • 2.2.7. Cortex-M33 Private Peripherals
  • Chapter 3. Processor Subsystem
    • 3.1. SIO
      • 3.1.1. Secure and Non-secure SIO
      • 3.1.2. CPUID
      • 3.1.3. GPIO Control
      • 3.1.4. Hardware Spinlocks
      • 3.1.5. Inter-processor FIFOs (Mailboxes)
      • 3.1.6. Doorbells
      • 3.1.7. Integer Divider
      • 3.1.8. RISC-V Platform Timer
      • 3.1.9. TMDS Encoder
      • 3.1.10. Interpolator
      • 3.1.11. List of Registers
    • 3.2. Interrupts
      • 3.2.1. Non-maskable Interrupt (NMI)
      • 3.2.2. Further Reading on Interrupts
    • 3.3. Event Signals (Arm)
    • 3.4. Event Signals (RISC-V)
    • 3.5. Debug
      • 3.5.1. Connecting to the SW-DP
      • 3.5.2. Arm Debug
      • 3.5.3. RISC-V Debug
      • 3.5.4. Debug Power Domains
      • 3.5.5. Software control of SWD pins
      • 3.5.6. Self-hosted Debug
      • 3.5.7. Trace
      • 3.5.8. Rescue Reset
      • 3.5.9. Security
      • 3.5.10. RP-AP
    • 3.6. Cortex-M33 Coprocessors
      • 3.6.1. GPIO Coprocessor (GPIOC)
      • 3.6.2. Double-precision Coprocessor (DCP)
      • 3.6.3. Redundancy Coprocessor (RCP)
      • 3.6.4. Floating Point Unit
    • 3.7. Cortex-M33 Processor
      • 3.7.1. Features
      • 3.7.2. Configuration
      • 3.7.3. Compliance
      • 3.7.4. Programmer’s model
      • 3.7.5. List of Registers
    • 3.8. Hazard3 Processor
      • 3.8.1. Instruction Set Reference
      • 3.8.2. Memory Access
      • 3.8.3. Memory Protection
      • 3.8.4. Interrupts and Exceptions
      • 3.8.5. Debug
      • 3.8.6. Custom Extensions
      • 3.8.7. Instruction Cycle Counts
      • 3.8.8. Configuration
      • 3.8.9. Control and Status Registers
    • 3.9. Arm/RISC-V Architecture Switching
      • 3.9.1. Automatic Switching
      • 3.9.2. Mixed Architecture Combinations
  • Chapter 4. Memory
    • 4.1. ROM
    • 4.2. SRAM
      • 4.2.1. Other On-chip Memory
    • 4.3. Boot RAM
      • 4.3.1. List of Registers
    • 4.4. External Flash and PSRAM (XIP)
      • 4.4.1. XIP Cache
      • 4.4.2. QSPI Memory Interface (QMI)
      • 4.4.3. Streaming DMA Interface
      • 4.4.4. Performance Counters
      • 4.4.5. List of XIP_CTRL Registers
      • 4.4.6. List of XIP_AUX Registers
    • 4.5. OTP
  • Chapter 5. Bootrom
    • 5.1. Bootrom Concepts
      • 5.1.1. Secure and Non-secure
      • 5.1.2. Partition Tables
      • 5.1.3. Flash Permissions
      • 5.1.4. Image Definitions
      • 5.1.5. Blocks And Block Loops
      • 5.1.6. Block Versioning
      • 5.1.7. A/B Versions
      • 5.1.8. Hashing and Signing
      • 5.1.9. Load Maps
      • 5.1.10. Packaged Binaries
      • 5.1.11. Anti-rollback Protection
      • 5.1.12. Flash Image Boot
      • 5.1.13. Flash Partition Boot
      • 5.1.14. Partition-Table-in-Image Boot
      • 5.1.15. Flash Boot Slots
      • 5.1.16. Flash Update Boot and Version Downgrade
      • 5.1.17. Try Before You Buy
      • 5.1.18. UF2 Targeting
      • 5.1.19. Address Translation
      • 5.1.20. Automatic Architecture Switching
    • 5.2. Processor-Controlled Boot Sequence
      • 5.2.1. Boot Outcomes
      • 5.2.2. Sequence
      • 5.2.3. POWMAN Boot Vector
      • 5.2.4. Watchdog Boot Vector
      • 5.2.5. RAM Image Boot
      • 5.2.6. OTP Boot
      • 5.2.7. Flash Boot
      • 5.2.8. BOOTSEL (USB/UART) Boot
      • 5.2.9. Boot Configuration (OTP)
    • 5.3. Launching Code On Processor Core 1
    • 5.4. Bootrom APIs
      • 5.4.1. Locating The API Functions
      • 5.4.2. API Function Availability
      • 5.4.3. API Function Return Codes
      • 5.4.4. API Functions And Exclusive Access
      • 5.4.5. SDK Access To The API
      • 5.4.6. Categorised List Of API Functions and ROM Data
      • 5.4.7. Alphabetical List Of API Functions and ROM Data
      • 5.4.8. API Function Listings
    • 5.5. USB Mass Storage Interface
      • 5.5.1. The RP2350 Drive
      • 5.5.2. UF2 Format Details
      • 5.5.3. UF2 Targeting Rules
    • 5.6. USB PICOBOOT Interface
      • 5.6.1. Identifying The Device
      • 5.6.2. Identifying The Interface
      • 5.6.3. Identifying The Endpoints
      • 5.6.4. PICOBOOT Commands
      • 5.6.5. Control Requests
    • 5.7. USB White-Labelling
      • 5.7.1. USB Device Descriptor
      • 5.7.2. USB Device Strings
      • 5.7.3. USB Configuration Descriptor
      • 5.7.4. MSD Drive
      • 5.7.5. UF2 INDEX.HTM File
      • 5.7.6. UF2 INFO_UF2.TXT File
      • 5.7.7. SCSI Inquiry
      • 5.7.8. Volume Label Simple Example
      • 5.7.9. Volume Label In-Depth Example
    • 5.8. UART Boot
      • 5.8.1. Baud Rate and Clock Requirements
      • 5.8.2. UART Boot Shell Protocol
      • 5.8.3. UART Boot Programming Flow
      • 5.8.4. Recovering from a Stuck Interface
      • 5.8.5. Requirements for UART Boot Binaries
    • 5.9. Metadata Block Details
      • 5.9.1. Blocks And block loops
      • 5.9.2. Common Block Items
      • 5.9.3. Image Definition Items
      • 5.9.4. Partition Table Items
      • 5.9.5. Minimum Viable Image Metadata
    • 5.10. Example Boot Scenarios
      • 5.10.1. Secure Boot
      • 5.10.2. Signed images
      • 5.10.3. Packaged Binaries
      • 5.10.4. A/B Booting
      • 5.10.5. A/B Booting with Owned Partitions
      • 5.10.6. Custom Bootloader
      • 5.10.7. OTP Bootloader
      • 5.10.8. Rollback Versions And Bootloaders
  • Chapter 6. Power
    • 6.1. Power Supplies
      • 6.1.1. Digital IO Supply (IOVDD)
      • 6.1.2. QSPI IO Supply (QSPI_IOVDD)
      • 6.1.3. Digital Core Supply (DVDD)
      • 6.1.4. USB PHY and OTP Supply (USB_OTP_VDD)
      • 6.1.5. ADC Supply (ADC_AVDD)
      • 6.1.6. Core Voltage Regulator Input Supply (VREG_VIN)
      • 6.1.7. On-Chip Voltage Regulator Analogue Supply (VREG_AVDD)
      • 6.1.8. Power Supply Sequencing
    • 6.2. Power Management
      • 6.2.1. Core Power Domains
      • 6.2.2. Power States
      • 6.2.3. Power State Transitions
    • 6.3. Core Voltage Regulator
      • 6.3.1. Operating Modes
      • 6.3.2. Software Control
      • 6.3.3. Power Manager Control
      • 6.3.4. Status
      • 6.3.5. Current Limit
      • 6.3.6. Over Temperature Protection
      • 6.3.7. Application Circuit
      • 6.3.8. External Components and PCB layout requirements
      • 6.3.9. List of Registers
    • 6.4. Power Management (POWMAN) Registers
    • 6.5. Power Reduction Strategies
      • 6.5.1. Top-level Clock Gates
      • 6.5.2. SLEEP State
      • 6.5.3. DORMANT State
      • 6.5.4. Memory Periphery Power Down
      • 6.5.5. Full Memory Power Down
      • 6.5.6. Programmer’s Model
  • Chapter 7. Resets
    • 7.1. Overview
    • 7.2. Changes from RP2040
    • 7.3. Chip Level Resets
      • 7.3.1. Chip-Level Reset table
      • 7.3.2. Chip-level Reset Destinations
      • 7.3.3. Chip-level Reset Sources
    • 7.4. System Resets (Power-on State Machine)
      • 7.4.1. Reset Sequence
      • 7.4.2. Register Control
      • 7.4.3. Interaction with Watchdog
      • 7.4.4. List of Registers
    • 7.5. Subsystem Resets
      • 7.5.1. Overview
      • 7.5.2. Programmer’s Model
      • 7.5.3. List of Registers
    • 7.6. Power-on Reset & Brownout Detection
      • 7.6.1. Power-on Reset (POR)
      • 7.6.2. Brownout Detection (BOD)
      • 7.6.3. Supply Monitor
      • 7.6.4. List of Registers
  • Chapter 8. Clocks
    • 8.1. Overview
      • 8.1.1. Clock sources
      • 8.1.2. Clock Generators
      • 8.1.3. Frequency Counter
      • 8.1.4. Resus
      • 8.1.5. Programmer’s Model
      • 8.1.6. List of Registers
    • 8.2. Crystal Oscillator (XOSC)
      • 8.2.1. Overview
      • 8.2.2. Changes from RP2040
      • 8.2.3. Usage
      • 8.2.4. Startup Delay
      • 8.2.5. XOSC Counter
      • 8.2.6. DORMANT mode
      • 8.2.7. Programmer’s Model
      • 8.2.8. List of Registers
    • 8.3. Ring Oscillator (ROSC)
      • 8.3.1. Overview
      • 8.3.2. Changes from RP2040
      • 8.3.3. ROSC/XOSC trade-offs
      • 8.3.4. Modifying the frequency
      • 8.3.5. Randomising the frequency
      • 8.3.6. ROSC divider
      • 8.3.7. Random Number Generator
      • 8.3.8. ROSC Counter
      • 8.3.9. DORMANT mode
      • 8.3.10. List of Registers
    • 8.4. Low Power Oscillator (LPOSC)
      • 8.4.1. Frequency Accuracy and Calibration
      • 8.4.2. Using an External Low Power Clock
      • 8.4.3. List of Registers
    • 8.5. Tick Generators
      • 8.5.1. Overview
      • 8.5.2. List of Registers
    • 8.6. PLL
      • 8.6.1. Overview
      • 8.6.2. Changes from RP2040
      • 8.6.3. Calculating PLL parameters
      • 8.6.4. Configuration
      • 8.6.5. List of Registers
  • Chapter 9. GPIO
    • 9.1. Overview
    • 9.2. Changes from RP2040
    • 9.3. Reset State
    • 9.4. Function Select
    • 9.5. Interrupts
    • 9.6. Pads
    • 9.7. Pad Isolation Latches
    • 9.8. Processor GPIO Controls (SIO)
    • 9.9. GPIO Coprocessor Port
    • 9.10. Software Examples
      • 9.10.1. Select an IO function
      • 9.10.2. Enable a GPIO interrupt
    • 9.11. List of Registers
      • 9.11.1. IO - User Bank
      • 9.11.2. IO - QSPI Bank
      • 9.11.3. Pad Control - User Bank
      • 9.11.4. Pad Control - QSPI Bank
  • Chapter 10. Security
    • 10.1. Overview (Arm)
      • 10.1.1. Secure Boot
      • 10.1.2. Encrypted Boot
      • 10.1.3. Isolating Trusted and Untrusted Software
    • 10.2. Processor Security Features (Arm)
      • 10.2.1. Background
      • 10.2.2. IDAU Address Map
    • 10.3. Overview (RISC-V)
    • 10.4. Processor Security Features (RISC-V)
    • 10.5. Secure Boot Enable Procedure
    • 10.6. Access Control
      • 10.6.1. GPIO Access Control
      • 10.6.2. Bus Access Control
      • 10.6.3. List of Registers
    • 10.7. DMA
      • 10.7.1. Channel Security Attributes
      • 10.7.2. Memory Protection Unit
      • 10.7.3. DREQ Attributes
      • 10.7.4. IRQ Attributes
    • 10.8. OTP
    • 10.9. Glitch Detector
      • 10.9.1. Theory of Operation
      • 10.9.2. Trigger Response
      • 10.9.3. List of Registers
    • 10.10. Factory Test JTAG
    • 10.11. Decommissioning
  • Chapter 11. PIO
    • 11.1. Overview
      • 11.1.1. Changes from RP2040
    • 11.2. Programmer’s Model
      • 11.2.1. PIO Programs
      • 11.2.2. Control Flow
      • 11.2.3. Registers
      • 11.2.4. Autopull
      • 11.2.5. Stalling
      • 11.2.6. Pin Mapping
      • 11.2.7. IRQ Flags
      • 11.2.8. Interactions Between State Machines
    • 11.3. PIO Assembler (pioasm)
      • 11.3.1. Directives
      • 11.3.2. Values
      • 11.3.3. Expressions
      • 11.3.4. Comments
      • 11.3.5. Labels
      • 11.3.6. Instructions
      • 11.3.7. Pseudoinstructions
    • 11.4. Instruction Set
      • 11.4.1. Summary
      • 11.4.2. JMP
      • 11.4.3. WAIT
      • 11.4.4. IN
      • 11.4.5. OUT
      • 11.4.6. PUSH
      • 11.4.7. PULL
      • 11.4.8. MOV (to RX)
      • 11.4.9. MOV (from RX)
      • 11.4.10. MOV
      • 11.4.11. IRQ
      • 11.4.12. SET
    • 11.5. Functional Details
      • 11.5.1. Side-set
      • 11.5.2. Program Wrapping
      • 11.5.3. FIFO Joining
      • 11.5.4. Autopush and Autopull
      • 11.5.5. Clock Dividers
      • 11.5.6. GPIO Mapping
      • 11.5.7. Forced and EXEC’d Instructions
    • 11.6. Examples
      • 11.6.1. Duplex SPI
      • 11.6.2. WS2812 LEDs
      • 11.6.3. UART TX
      • 11.6.4. UART RX
      • 11.6.5. Manchester Serial TX and RX
      • 11.6.6. Differential Manchester (BMC) TX and RX
      • 11.6.7. I2C
      • 11.6.8. PWM
      • 11.6.9. Addition
      • 11.6.10. Further Examples
    • 11.7. List of Registers
  • Chapter 12. Peripherals
    • 12.1. UART
      • 12.1.1. Overview
      • 12.1.2. Functional description
      • 12.1.3. Operation
      • 12.1.4. UART hardware flow control
      • 12.1.5. UART DMA Interface
      • 12.1.6. Interrupts
      • 12.1.7. Programmer’s Model
      • 12.1.8. List of Registers
    • 12.2. I2C
      • 12.2.1. Features
      • 12.2.2. IP Configuration
      • 12.2.3. I2C Overview
      • 12.2.4. I2C Terminology
      • 12.2.5. I2C Behaviour
      • 12.2.6. I2C Protocols
      • 12.2.7. TX FIFO Management and START, STOP and RESTART Generation
      • 12.2.8. Multiple Master Arbitration
      • 12.2.9. Clock Synchronization
      • 12.2.10. Operation Modes
      • 12.2.11. Spike Suppression
      • 12.2.12. Fast Mode Plus Operation
      • 12.2.13. Bus Clear Feature
      • 12.2.14. IC_CLK Frequency Configuration
      • 12.2.15. DMA Controller Interface
      • 12.2.16. Operation of Interrupt Registers
      • 12.2.17. List of Registers
    • 12.3. SPI
      • 12.3.1. Changes from RP2040
      • 12.3.2. Overview
      • 12.3.3. Functional Description
      • 12.3.4. Operation
      • 12.3.5. List of Registers
    • 12.4. ADC and Temperature Sensor
      • 12.4.1. Changes from RP2040
      • 12.4.2. ADC controller
      • 12.4.3. SAR ADC
      • 12.4.4. ADC ENOB
      • 12.4.5. INL and DNL
      • 12.4.6. Temperature Sensor
      • 12.4.7. List of Registers
    • 12.5. PWM
      • 12.5.1. Overview
      • 12.5.2. Programmer’s Model
      • 12.5.3. List of Registers
    • 12.6. DMA
      • 12.6.1. Changes from RP2040
      • 12.6.2. Configuring Channels
      • 12.6.3. Triggering Channels
      • 12.6.4. Data Request (DREQ)
      • 12.6.5. Interrupts
      • 12.6.6. Security
      • 12.6.7. Bus Error Handling
      • 12.6.8. Additional Features
      • 12.6.9. Example Use Cases
      • 12.6.10. List of Registers
    • 12.7. USB
      • 12.7.1. Overview
      • 12.7.2. Changes from RP2040
      • 12.7.3. Architecture
      • 12.7.4. Programmer’s Model
      • 12.7.5. List of Registers
    • 12.8. System Timers
      • 12.8.1. Overview
      • 12.8.2. Counter
      • 12.8.3. Alarms
      • 12.8.4. Programmer’s Model
      • 12.8.5. List of Registers
    • 12.9. Watchdog
      • 12.9.1. Overview
      • 12.9.2. Changes from RP2040
      • 12.9.3. Watchdog Counter
      • 12.9.4. Control Watchdog Reset Levels
      • 12.9.5. Scratch Registers
      • 12.9.6. Programmer’s Model
      • 12.9.7. List of Registers
    • 12.10. Always-On Timer
      • 12.10.1. Overview
      • 12.10.2. Changes from RP2040
      • 12.10.3. Accessing the AON Timer
      • 12.10.4. Using the Alarm
      • 12.10.5. Selecting the AON Timer Tick Source
      • 12.10.6. Synchronising the AON Timer to an External 1Hz Clock
      • 12.10.7. Using an external clock or tick from GPIO
      • 12.10.8. Using a Tick Faster than 1ms
      • 12.10.9. List of Registers
    • 12.11. HSTX
      • 12.11.1. Data FIFO
      • 12.11.2. Output Shift Register
      • 12.11.3. Bit Crossbar
      • 12.11.4. Clock Generator
      • 12.11.5. Command Expander
      • 12.11.6. PIO-to-HSTX Coupled Mode
      • 12.11.7. List of Control Registers
      • 12.11.8. List of FIFO Registers
    • 12.12. TRNG
      • 12.12.1. Overview
      • 12.12.2. Configuration
      • 12.12.3. Operation
      • 12.12.4. Caveats
      • 12.12.5. List of Registers
    • 12.13. SHA-256 Accelerator
      • 12.13.1. Message Padding
      • 12.13.2. Throughput
      • 12.13.3. Data Size and Endianness
      • 12.13.4. DMA DREQ Interface
      • 12.13.5. List of Registers
    • 12.14. QSPI Memory Interface (QMI)
      • 12.14.1. Overview
      • 12.14.2. QSPI Transfers
      • 12.14.3. Timing
      • 12.14.4. Address Translation
      • 12.14.5. Direct Mode
      • 12.14.6. List of Registers
    • 12.15. System Control Registers
      • 12.15.1. SYSINFO
      • 12.15.2. SYSCFG
      • 12.15.3. TBMAN
      • 12.15.4. BUSCTRL
  • Chapter 13. OTP
    • 13.1. OTP Address Map
      • 13.1.1. Guarded Reads
    • 13.2. Background: OTP IP Details
    • 13.3. Background: OTP Hardware Architecture
      • 13.3.1. Lock Shim
      • 13.3.2. External Interfaces
      • 13.3.3. OTP Boot Oscillator
      • 13.3.4. Power-up State Machine
    • 13.4. Critical Flags
    • 13.5. Page Locks
      • 13.5.1. Lock Progression
      • 13.5.2. OTP Access Keys
      • 13.5.3. Lock Encoding in OTP
      • 13.5.4. Special Pages
      • 13.5.5. Permissions of Blank Devices
    • 13.6. Error Correction Code (ECC)
      • 13.6.1. Bit repair by polarity (BRP)
      • 13.6.2. Modified Hamming ECC
    • 13.7. Device Decommissioning (RMA)
    • 13.8. List of Registers
    • 13.9. Predefined OTP Data Locations
  • Chapter 14. Electrical and Mechanical
    • 14.1. QFN-60 Package
      • 14.1.1. Thermal characteristics
      • 14.1.2. Recommended PCB Footprint
    • 14.2. QFN-80 Package
      • 14.2.1. Thermal characteristics
      • 14.2.2. Recommended PCB Footprint
    • 14.3. Flash in Package
    • 14.4. Package Markings
    • 14.5. Storage conditions
    • 14.6. Solder profile
    • 14.7. Compliance
    • 14.8. Pinout
      • 14.8.1. Pin Locations
      • 14.8.2. Pin Definitions
    • 14.9. Electrical Specifications
      • 14.9.1. Absolute Maximum Ratings
      • 14.9.2. ESD Performance
      • 14.9.3. Thermal Performance
      • 14.9.4. IO Electrical Characteristics
      • 14.9.5. Power Supplies
      • 14.9.6. Core Voltage Regulator
      • 14.9.7. Power Consumption
  • Appendix A: Register Field Types
    • Changes from RP2040
    • Standard types
      • RW:
      • RO:
      • WO:
    • Clear types
      • SC:
      • WC:
    • FIFO types
      • RWF:
      • RF:
      • WF:
  • Appendix B: Units Used in This Document
    • Memory and Storage Capacity
    • Transfer Rate
    • Physical Quantities
    • Scale Prefixes
    • Digit Separators
  • Appendix E: Errata
    • ACCESSCTRL
      • RP2350-E3
    • Bootrom
      • RP2350-E10
    • DMA
      • RP2350-E5
      • RP2350-E8
    • GPIO
      • RP2350-E9
    • Hazard3
      • RP2350-E4
      • RP2350-E6
      • RP2350-E7
    • SIO
      • RP2350-E1
      • RP2350-E2
  • Appendix H: Documentation Release History
    • August 8 2024